| Name : ver
| |
| Version : 0.98
| Vendor : Red Hat Software
|
| Release : 1
| Date : 1998-10-27 02:19:28
|
| Group : Development/Building
| Source RPM : ver-0.98-1.src.rpm
|
| Size : 0.30 MB
| |
| Packager : Red Hat Software < bugs_redhat_com>
| |
| Summary : A structural Verilog compiler.
|
Description :
Ver is a subset of the Verilog Hardware Description Language.
Ver incorporates the structural elements of the language, but not the
behavioral ones. Ver should be used to generate netlists in the form of IVF
files for a separate logic simulator (ver itself is not a simulator). Vsim,
a stand-alone simulator, is included for testing of logic designs and can
handle 0, 1, x, and z logic levels. Cyco, a cycle simulation compiler, is
also included and is used to compile netlists into fast C code.
If you don\'t know what any of this means, you probably don\'t need to install
ver...
|
